The device and method described relate generally to storage devices, and more particularly, the device and method relate to flip-flops.
Advances in integrated circuit technology and design have led to a rapid increase in integrated circuit performance. A good example of this increase in performance can be seen in microprocessors. Only a few years ago, state-of-the-art microprocessors shipped with personal computers had clock rates of around 60 MHz. Today, personal computers are commonly shipped with microprocessors having clock rates of 2 GHz or more. Accordingly, it would be desirable to increase the speed of computers, microprocessors and digital circuits
A latch and flip-flop circuit is described having a reduced clock-to-Q delay. Additionally, the latch and flip-flop has a reduced set-up time. Set-up time is the minimum time required between a data input and the clock. Reductions in clock-to-Q delay and set-up time may result in increased microprocessor clock speeds and higher performance computer systems.
The latch and flip-flop circuits may have both a data input signal and a complement data input signal. The data input signal and the complement data input signals are selectively connected to opposite sides of a pair of cross-coupled storage devices of the latch or flip-flop to function as a storage device. The data input signal may be coupled to the storage device via a transmission gate, switch or the like. The transmission gate or switch may be controlled by an enable signal such as a clock signal. When the transmission gate or switch is enabled, the data input signal overrides the complement storage device output signal. Similarly, the complement data input signal overrides the storage device output signal.
Because the data input signal overrides the complement storage device output signal, and the complement data input signal overrides the storage device output signal, the set up time and the clock-to-Q time may be reduced relative to conventional devices. In addition, because the data input signal and the complement data input signal drive opposite sides of the pair of cross-coupled gates, each through a single logic gate, the state of the pair of cross-coupled gates can be set in only one gate delay. This helps reduce the clock-to-Q time, as well as the set-up time. In one embodiment, the set-up time of the master latch is equal to the gate delay of the transmission gate at the input to the master latch.
In a first illustrative embodiment, the data input signal and the complement data input signal are provided to a first switch and a second switch, respectively, of the latch circuit. Each of the first and second switches may for example, have a transmission gate or an inverter type gate having a tri-stateable output. The state of the output of each of the inverter type gates may be controlled by an enable signal such as a clock signal. When the first switch and the second switch are enabled, the first switch passes the data input signal to a first side of a pair of cross-coupled inverters and the second switch passes the complement data input signal to a second opposite side of the cross-coupled inverters. The latch preferably has a data output terminal that corresponds to the output of the first side of the cross-coupled inverters and a complement data output terminal that corresponds to the output of the second side of the cross-coupled inverters.
An illustrative master-slave flip-flop of the present invention combines two of the latch circuits discussed above. In this embodiment, the data output terminal of the master latch is connected to a data input terminal of the slave latch, and the complement data output terminal of the master latch is connected to the complement data input terminal of the slave latch. For a positive edge triggered flip-flop, the first and second switch elements of the master latch are enabled when the clock signal transitions from a high state to a low state, and the first and second switch elements of the slave latch are enabled when the clock signal transitions from a low state to a high state.
It is contemplated that each of the first and second switch elements of the master latch and slave latch may be implemented in a number of ways. For example, each of the first and second switch elements may be formed from a single transistor, with the gate of the single transistor coupled to the clock signal. Alternatively, each of the first and second switch elements may be formed from a transmission gate. The transmission gate may have an n-channel transistor an d a p-channel transistor, with the gate of the n-channel transistor coupled to a clock signal and the gate of the p-channel transistor coupled to a complement clock signal, or visa versa. Further still, the first and second switch elements may be formed from an inverter type transistor gate having a tri-stateable output, with the state of the output controlled by a clock and/or complement clock signal delayed by one transistor delay. In this latter case, the switching function of the first and second switch elements may be combined into a single circuit, which as described below, may reduce the number of transistors required to form the switching element circuits.